1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. In particular, embodiments of the invention relate to a semiconductor memory device comprising two rows of pads.
This application claims priority to Korean Patent Application No. 10-2006-0013767, filed on Feb. 13, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A semiconductor memory device can simultaneously input multiple bits of data to or simultaneously output multiple bits of data from a memory cell array in accordance with a data input/output mode of the semiconductor memory device. For example, when the data input/output mode of a semiconductor memory device is a ×4 mode, the semiconductor memory device simultaneously inputs or outputs four bits of data, and when the data input/output mode of a semiconductor memory device is a ×8 mode, the semiconductor memory device simultaneously inputs or outputs eight bits of data. A single semiconductor memory device can operate in any one of a plurality of data input/output modes, and the mode in which the semiconductor memory device operates may depend on whether a pad of a memory chip in the semiconductor memory device was bonded to a package pin of the semiconductor memory device during the fabrication of the semiconductor memory device.
Figure (FIG.) 1 shows a conventional semiconductor memory device.
Referring to FIG. 1, a conventional semiconductor memory device 1 comprises a first row of pads 10, a second row of pads 20, a first input/output multiplexer 30 associated with first row of pads 10, and a second input/output multiplexer 40 associated with second row of pads 20. The data input/output mode in which first and second input/output multiplexers 30 and 40 operate changes in response to an input/output mode control signal PX.
However, in the related art, the row of pads, among first and second rows of pads 10 and 20, to which data DATA0 (which is stored in a memory cell array) is output may be changed in accordance with the data input/output mode. For example, as shown in FIG. 1 and illustrated by different types of arrows, data DATA0 is output to first row of pads 10 in the ×4 mode. Alternatively, data DATA0 may be output to second row of pads 20 in the ×8 mode.
Therefore, in conventional semiconductor memory device 1, it is necessary for first input/output multiplexer 30 to be electrically connected to second row of pads 20 as well as first row of pads 10, and it is necessary for second input/output multiplexer 40 to be electrically connected to first row of pads 10 as well as second row of pads 20. For example, a vertical bus 50 may be formed between first input/output multiplexer 30 and second input/output multiplexer 40 in order to connect the multiplexers. When data passes through vertical bus 50, additional loading is performed compared to when data does not pass through vertical bus 50. Thus, data input/output characteristics (for example, a frequency characteristic) of conventional semiconductor memory device 1 may suffer (i.e., deteriorate).